The present invention relates to a solution to reduce a noise output due to spurious generated in a semiconductor integrated circuit (hereinafter also abbreviated as “IC”) used in a broadcast receiver.
In recent years, as semiconductor integrated circuit technology has advanced, radio-frequency (RF), intermediate-frequency (IF), and baseband signal processing functions required for a receiver tend to be integrated onto a single IC chip. For example, a digital broadcast receiver for a broadcast service called “One Seg,” incorporated in a mobile phone, integrates components ranging from an RF circuit to an OFDM demodulation section onto a same IC, thereby facilitating a further size reduction.
However, integration of these functions onto a single IC chip has caused unwanted emission (spurious) generated in the IC to be introduced into an RF amplifier circuit etc., in addition to a received signal, thereby producing a significant effect on the reception function. Conventionally, a superheterodyne architecture has caused a degradation in reception performance due to a beat output etc. by an IF signal generated from an output of a local oscillator and a received signal. To make matters worse, with an increase in the integration degree, a beat component between an oscillator signal of a crystal oscillator, used as an internal reference signal source, and an output of a local oscillator, and in addition, a noise component due to a logic signal caused by integration of a logic circuit onto a same chip, may be introduced to the RF circuit, thereby causing a degradation in receiver sensitivity etc. Therefore, the quality of the device as a receiver may be significantly degraded, and thus there has been a strong need to reduce such noise due to spurious.
A conventional semiconductor integrated circuit for a receiver is described below using FIG. 9.
FIG. 9 is a block diagram of a semiconductor integrated circuit used for a conventional receiver.
In FIG. 9, reference numeral 1 denotes an antenna circuit, including a tuner circuit or a filter circuit, a gain adjustment circuit, and a matching circuit. Reference numeral 2 denotes an RF circuit, including a low noise amplifier or a gain control amplifier etc. Reference numeral 3 denotes a mixer; 5, an IF signal or a baseband signal processing circuit; 6, a local oscillator circuit; 7, a frequency divider; 8, a PLL circuit; and 17, an oscillator which generates a reference frequency signal used in the PLL circuit 8 etc., and the oscillator is usually implemented by a crystal oscillator. Reference numeral 12 denotes an input terminal; 18, an output terminal; and 200, a digital signal processing circuit for demodulation, which demodulates a baseband signal by analog or digital signal processing, and outputs the result to a downstream component. Reference numeral 100 denotes an IC including all of the component circuits described above. Note that the RF circuit 2 and the digital signal processing circuit for demodulation 200 may be included in or disposed on a chip other than the IC 100.
FIG. 10 illustrates a schematic layout on a conventional IC chip.
In FIG. 10, reference numeral 31 denotes a received-signal input terminal; 44, a ground terminal; 32, a wire connecting the received-signal input terminal 31 to a bonding pad 33 on the IC chip 35; 33 and 45, bonding pads; 40, a line connecting the bonding pad 33 to a circuit block 36 on the IC chip 35; and 36, an RF signal block, including the RF circuit 2, the mixer 3, etc. of FIG. 9. Reference numeral 43 denotes a block which functions as a noise signal source, and is a crystal oscillator or a logic circuit etc. Reference numeral 35 denotes the IC chip; and 34, the IC package. Although the noise signal source block 43 is usually disposed spaced apart from the circuit block 36, a noise component propagates through a parasitic capacitive element etc. as is shown by arrows 38 and 39, and enter the circuit block 36. A dependence on the parasitic element allows noise to enter any part of the circuit block 36; however, the effect of noise is maximum when the noise enters the input terminal, in which case a high gain is provided at the signal output.
The operation of a conventional receiver configured as described above will now be described.
In FIG. 9, a broadcast signal is input through an antenna 11 to the antenna circuit 1, in which a desired frequency is selected and unwanted signals are filtered out, and then the broadcast signal is input through the input terminal 12 to the IC 100. The input broadcast signal (i.e., the received signal) is amplified or attenuated in the RF circuit 2, and then is input to the mixer 3. The mixer 3 extracts an IF signal having a desired signal bandwidth from an output from the local oscillator circuit 6 and from the received signal, and inputs the IF signal to the IF signal processing circuit 5. An output of the IF signal processing circuit 5 is input to the digital signal processing circuit for demodulation 200, which produces a video or audio signal etc. by demodulation. Meanwhile, an output of the local oscillator circuit 6 is input through the frequency divider 7 to the PLL circuit 8, which operates so as to obtain a local oscillation output having a desired frequency. Although the intermediate frequency IF is usually set to an out-of-baseband bandwidth frequency, the mixer 3 may directly generate a baseband signal.
Here, the RF circuit 2 and the mixer 3 may receive, in addition to the received signal input from the antenna circuit 1, an unwanted noise component (spurious component) generated in the IC 100 through a parasitic element in the IC 100. The spurious component is amplified and mixed together with the received signal to generate an IF signal, and the IF signal is demodulated in the digital signal processing circuit for demodulation 200; thus, the reception characteristic may be affected. Major sources of spurious noise include harmonic components contained in the output of the crystal oscillator 17 and switching noise from the logic circuit having a wide frequency range; and steps have previously been taken.
Patent Document 1 listed below describes technology in which blocks on an IC are arranged such that a noise source block and the RF block are disposed apart from each other, with an interference reduction block therebetween, in order to reduce interference.
However, although this conventional method allows the spurious to be reduced, a configuration in which a multitude of blocks are arranged on the IC chip of several millimeters square makes it difficult to completely remove the effects of parasitic components.
In addition, technology described in Patent Document 2 listed below changes the frequency of the local oscillation so that the frequency of the generated spurious will not fall within the receiving bandwidth in order to shift the IF frequency. However, although this method allows the effects of spurious to be reduced, a shift of the frequency of the IF signal results in a side effect of decrease in the reception characteristic (e.g., sensitivity, interference characteristic, etc.).
The referenced Patent Documents are as follows:    Patent Document 1: Japanese Examined Patent Publication No. H6-066415    Patent Document 2: Japanese Patent Publication No. 2006-042054